Two storage devices each including a controller module (CM) are communicably interconnected through a Peripheral Component Interconnect Express (PCIe) bus. The PCIe bus is used with a plurality of transmission paths (lanes) being bundled together. A lane refers to a combination of a transmitting communication line and a receiving communication line from one CM to another CM.
Related techniques are discussed in Japanese Laid-open Patent Publication No. 2007-312095, Japanese Laid-open Patent Publication No. 2001-217896, and Japanese Laid-open Patent Publication No. 2009-93636.